TSMC is actively progressing with the development of its 1.4nm-class manufacturing technology, named A14, as revealed during the IEEE International Electron Devices Meeting.
The company has not disclosed the start date for high-volume manufacturing or the specifications of A14.
Mass production using TSMC's 2nm-class fabrication process is still on track for 2025.
A14 is anticipated to utilize 2nd or 3rd generation gate-all-around FETs, as TSMC explores vertically-stacked CFETs. The nodes, including N2 and A14, will require system-level co-optimization for improved performance, power, and features.
Whether TSMC plans to adopt High-NA EUV lithography tools for A14 remains uncertain, with potential challenges for chip designers and manufacturers.
TSMC's focus on next-gen production nodes indicates ongoing efforts by its scientists and developers.
